From 14222d86785d89415c014dab294205fd186b7084 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 5 Aug 2019 15:10:18 +0300 Subject: arch/x86: Change smm_subregion() prototype MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do this to avoid some amount of explicit typecasting that would be required otherwise. Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/denverton_ns/cpu.c | 8 ++++---- src/soc/intel/denverton_ns/memmap.c | 13 +++++-------- src/soc/intel/denverton_ns/romstage.c | 6 ++---- 3 files changed, 11 insertions(+), 16 deletions(-) (limited to 'src/soc/intel/denverton_ns') diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index d6ddcc0548..067f59fb3a 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -126,9 +126,9 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* All range registers are aligned to 4KiB */ @@ -138,12 +138,12 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, smm_region(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - relo_attrs.smbase = (uint32_t)smm_base; + relo_attrs.smbase = smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index d94d1f3ddd..d4265e994e 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -70,21 +70,19 @@ static inline size_t smm_region_size(void) return system_agent_region_base(TOLUD) - smm_region_start(); } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - sub_base = smm_region_start(); - sub_size = smm_region_size(); - + smm_region(&sub_base, &sub_size); assert(sub_size > CONFIG_SMM_RESERVED_SIZE); switch (sub) { @@ -101,8 +99,7 @@ int smm_subregion(int sub, void **start, size_t *size) return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; - return 0; } diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 6950620a87..53c51f488c 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -141,9 +141,8 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; uintptr_t top_of_ram; - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uintptr_t tseg_base; console_init(); @@ -183,8 +182,7 @@ asmlinkage void car_stage_entry(void) */ if (CONFIG(HAVE_SMI_HANDLER)) { smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); } run_postcar_phase(&pcf); -- cgit v1.2.3