From 88164787ee7e7d9e13d5a9b95093fd70394ddc46 Mon Sep 17 00:00:00 2001 From: Patrick Havelange Date: Tue, 18 Jun 2019 12:15:07 +0200 Subject: soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The value for that macro should be 1<<19. This is confirmed by the Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE. See Intel Atom® Processor C3000 Product Family Datasheet (February 2018) : https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-series/c3000-family-datasheet.html Signed-off-by: Patrick Havelange Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33573 Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Reviewed-by: David Guckian Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/include/soc/gpio_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/denverton_ns/include') diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h index 43e0647bd0..ae61e6d7c4 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h @@ -182,7 +182,7 @@ #define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01 // GPIO Input Route SCI -#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 10) +#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 19) #define N_PCH_GPIO_RX_SCI_ROUTE 19 #define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00 #define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01 -- cgit v1.2.3