From 053ea606828afecbabf458beb575272dccdd8a36 Mon Sep 17 00:00:00 2001 From: Julien Viard de Galbert Date: Wed, 7 Mar 2018 14:18:49 +0100 Subject: soc/intel/denverton_ns: Configure MCA Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba Signed-off-by: Julien Viard de Galbert Reviewed-on: https://review.coreboot.org/c/25433 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/include/soc/msr.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel/denverton_ns/include') diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 825d4cfca8..1b27eefcaa 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -25,6 +25,11 @@ #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c +#define IA32_MCG_CAP 0x179 +#define IA32_MCG_CAP_COUNT_MASK 0xff +#define IA32_MCG_CAP_CTL_P_BIT 8 +#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT) +#define IA32_MCG_CTL 0x17b #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -- cgit v1.2.3