From c126084bc53e0f74f6085f4f84b5bc387d701a4f Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 23 Apr 2019 15:18:51 -0600 Subject: soc/intel: Add GPI interrupt config register offset info Add the offset information for GPI interrupt status and enable register in the pad_community structure. Populate the concerned information for individual SoCs. This offset information is required to clear the interrupt configuration during the bootup. BUG=b:130593883 BRANCH=None TEST=Ensure that the interrupt configuration are cleared during bootup. Ensured that the system boots to ChromeOS. Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/32446 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/denverton_ns/gpio.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/intel/denverton_ns/gpio.c') diff --git a/src/soc/intel/denverton_ns/gpio.c b/src/soc/intel/denverton_ns/gpio.c index 7c45d40de5..64099583a3 100644 --- a/src/soc/intel/denverton_ns/gpio.c +++ b/src/soc/intel/denverton_ns/gpio.c @@ -58,6 +58,8 @@ static const struct pad_community dnv_gpio_communities[] = { NUM_SC0_GPI_REGS, .pad_cfg_base = R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_SC1_PAD_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -75,6 +77,8 @@ static const struct pad_community dnv_gpio_communities[] = { .gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS, .pad_cfg_base = R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_SC0_PAD_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -92,6 +96,8 @@ static const struct pad_community dnv_gpio_communities[] = { .gpi_status_offset = NUM_NC_GPI_REGS, .pad_cfg_base = R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -109,6 +115,8 @@ static const struct pad_community dnv_gpio_communities[] = { .gpi_status_offset = 0, .pad_cfg_base = R_PCH_PCR_GPIO_NC_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_NC_PAD_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, -- cgit v1.2.3