From 053ea606828afecbabf458beb575272dccdd8a36 Mon Sep 17 00:00:00 2001 From: Julien Viard de Galbert Date: Wed, 7 Mar 2018 14:18:49 +0100 Subject: soc/intel/denverton_ns: Configure MCA Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba Signed-off-by: Julien Viard de Galbert Reviewed-on: https://review.coreboot.org/c/25433 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/cpu.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'src/soc/intel/denverton_ns/cpu.c') diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index b3a12c5cad..ce6df68f9f 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -35,12 +35,41 @@ static struct smm_relocation_attrs relo_attrs; +static void dnv_configure_mca(void) +{ + msr_t msr; + int num_banks; + struct cpuid_result cpuid_regs; + + /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE + * and CPUID.(EAX=1):EDX[14]==1 MCA*/ + cpuid_regs = cpuid(1); + if ((cpuid_regs.edx & (1<<7 | 1<<14)) != (1<<7 | 1<<14)) + return; + + msr = rdmsr(IA32_MCG_CAP); + num_banks = msr.lo & IA32_MCG_CAP_COUNT_MASK; + if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) { + /* Enable all error logging */ + msr.lo = msr.hi = 0xffffffff; + wrmsr(IA32_MCG_CTL, msr); + } + + /* TODO(adurbin): This should only be done on a cold boot. Also, some + of these banks are core vs package scope. For now every CPU clears + every bank. */ + mca_configure(NULL); +} + static void denverton_core_init(struct device *cpu) { msr_t msr; printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n"); + /* Clear out pending MCEs */ + dnv_configure_mca(); + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; -- cgit v1.2.3