From 46e68ac99adb0a7c83c39842679636081c4d77a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 4 Nov 2019 22:07:29 +0100 Subject: soc/intel/denverton_ns: make use of common cbmem_top_chipset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This replaces denverton_ns's own implementation of cbmem_top_chipset and selects the common code one. Change-Id: Idae96aabe2807e465bb7ab0f29910757d0346ce9 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36619 Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/denverton_ns/Kconfig') diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index cb3713d3b0..b7d3d1affd 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES # select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR -- cgit v1.2.3