From fe2ac34d956d9370949336e31d8a21576114deaa Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Tue, 31 Aug 2021 21:14:52 +0530 Subject: soc/intel/common: Add PMC IPC commands for FIVR Add PMC IPC commands information for FIVR control functionality. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/57095 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/include/intelblocks/pmc_ipc.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h index b67abc0fcd..fb33a075ee 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -16,6 +16,15 @@ #define PMC_IPC_CMD_SIZE_SHIFT 16 #define PMC_IPC_CMD_SIZE_MASK 0xff +/* IPC command to control FIVR Configuration */ +#define PMC_IPC_CMD_COMMAND_FIVR 0xA3 +/* IPC subcommand to write FIVR Register */ +#define PMC_IPC_CMD_CMD_ID_FIVR_WRITE 0x01 +/* IPC subcommand to control RFI Control 0 register logic write */ +#define PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC 0x00 +/* IPC subcommand to control RFI Control 4 register logic write */ +#define PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC 0x01 + #define PMC_IPC_CMD_FIELD(name, val) \ ((((val) & PMC_IPC_CMD_##name##_MASK) << PMC_IPC_CMD_##name##_SHIFT)) -- cgit v1.2.3