From f699c14c03a78549b0e5ed32cf9714473127c618 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 8 Jun 2018 17:57:37 +0530 Subject: soc/intel/common/block/cpu: Add option to skip coreboot AP init SoC users from IOTG team is looking forward for a solution to skip coreboot AP initialization flow and make use of FSPS-UPD to perform AP reset. TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs out of reset. Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/26644 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/chip/chip.c | 15 +++++++++++++++ src/soc/intel/common/block/cpu/mp_init.c | 7 +++++++ src/soc/intel/common/block/include/intelblocks/chip.h | 15 +++++++++++++++ 3 files changed, 37 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index cfec4eca39..aecf060e3f 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -32,3 +32,18 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void) return soc_config; } + +/* + * This function will get MP Init config + * + * Return values: + * 0 = Make use of coreboot MP Init + * 1 = Make use of FSP MP Init + */ +int chip_get_fsp_mp_init(void) +{ + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + return common_config->use_fsp_mp_init; +} diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index e264348055..fd0ac992b5 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -124,6 +125,9 @@ static void init_cpus(void *unused) struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); assert(dev != NULL); + if (chip_get_fsp_mp_init()) + return; + microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); @@ -138,6 +142,9 @@ static void wrapper_x86_setup_mtrrs(void *unused) /* Ensure to re-program all MTRRs based on DRAM resource settings */ static void post_cpus_init(void *unused) { + if (chip_get_fsp_mp_init()) + return; + if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 1000) < 0) printk(BIOS_ERR, "MTRR programming failure\n"); diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h index 555bdaa893..d761f6be76 100644 --- a/src/soc/intel/common/block/include/intelblocks/chip.h +++ b/src/soc/intel/common/block/include/intelblocks/chip.h @@ -33,9 +33,24 @@ struct soc_intel_common_config { int chipset_lockdown; struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + /* + * Option for mainboard to skip coreboot MP initialization + * 0 = Make use of coreboot MP Init + * 1 = Make use of FSP MP Init + */ + uint8_t use_fsp_mp_init; }; /* This function to retrieve soc config structure required by common code */ const struct soc_intel_common_config *chip_get_common_soc_structure(void); +/* + * This function will get MP Init config + * + * Return values: + * 0 = Make use of coreboot MP Init + * 1 = Make use of FSP MP Init + */ +int chip_get_fsp_mp_init(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */ -- cgit v1.2.3