From ddd66ed204f47850d3f3a607344ec5f20a15528a Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Thu, 23 Jun 2022 22:14:28 +0530 Subject: common/block/cse: Add Kconfigs to indicate when CSE FW sync is performed CSE FW sync is currently performed in romstage, when uncompressed ME_RW blobs are used. When compressed blobs are used, this has to be done in post-RAM stages. Add Kconfigs to describe when the CSE FW sync will be performed, in romstage or in ramstage. BRANCH=firmware-brya-14505.B Change-Id: Iac37aaa5ede5e1cd2d76a58ce2db9cb5b8f42398 Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/65366 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cse/Kconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 9621e9ad5f..55a2b49194 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -173,6 +173,20 @@ config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY Mainboard user to select this Kconfig in order to capture pre-cpu reset boot performance telemetry data. +config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE + bool + default y + depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW + help + Use default flow of CSE FW Update in romstage when uncompressed ME_RW blobs are used. + +config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE + bool + default n + depends on SOC_INTEL_CSE_LITE_COMPRESS_ME_RW + help + Use this option for CSE FW Update when compressed blobs are used. + if STITCH_ME_BIN config CSE_COMPONENTS_PATH -- cgit v1.2.3