From dbcf293211df0d698c0d14b8668f55dd8be36ed3 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 28 Nov 2018 15:29:00 +0100 Subject: soc/intel/common/lpc_lib: Add function to disable LPC Clock Run Needed to fix up FSP-S bug on Apollo Lake. Change-Id: If09fee07debb1f0de840b0c0bd7a65d338665f7c Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/29898 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Aaron Durbin --- src/soc/intel/common/block/include/intelblocks/lpc_lib.h | 2 ++ src/soc/intel/common/block/lpc/lpc_lib.c | 6 ++++++ 2 files changed, 8 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index e7b844fc4a..f77b8d5d71 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -97,6 +97,8 @@ void lpc_set_eiss(void); void lpc_set_serirq_mode(enum serirq_mode mode); /* Enable CLKRUN_EN for power gating LPC. */ void lpc_enable_pci_clk_cntl(void); +/* LPC Clock Run is a feature to stop LPC clock unless a peripheral objects. */ +void lpc_disable_clkrun(void); /* * Setup I/O Decode Range Register for LPC * ComA Range 3F8h-3FFh [2:0] diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index d27f877c85..bcbd8e6cbd 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -301,3 +301,9 @@ void lpc_enable_pci_clk_cntl(void) { pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN); } + +void lpc_disable_clkrun(void) +{ + const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL); + pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN); +} -- cgit v1.2.3