From d643165c64ef89c72e4e004abe7a7675f90b0955 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 13 Apr 2022 20:30:53 +0530 Subject: soc/intel/cmn/fast_spi: Add API to set SPI controller VCL This patch creates a helper function to set SPI controller VCL bit as recommended by Intel Flash Security Specification. BUG=b:211954778 TEST=Able to build google/brya and verified that SPI flash controller MMIO register 0xC4 bit 30 is set. Signed-off-by: Subrata Banik Change-Id: Ie9a12db1bab81779fd8e7db90221d08da3c65011 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63626 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: Werner Zeh --- src/soc/intel/common/block/fast_spi/fast_spi.c | 17 +++++++++++++++++ src/soc/intel/common/block/fast_spi/fast_spi_def.h | 7 +++++++ .../intel/common/block/include/intelblocks/fast_spi.h | 4 ++++ 3 files changed, 28 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 4ff1e9ba70..7e8a1a2844 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -170,6 +170,23 @@ void fast_spi_pr_dlock(void) write32(spibar + SPIBAR_DLOCK, dlock); } +/* + * Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30). + */ +void fast_spi_vscc0_lock(void) +{ + void *spibar = fast_spi_get_bar(); + + /* + * SPI Flash Programming Guide Section 5.5.2 describes Vendor Component Lock (VCL). + * It is recommended to set the VCL bit. VCL applies to both VSCC0 and VSCC1. + * Without this bit being set, it is possible to modify Host/GbE VSCC register(s), + * which might results in undesired host and integrated GbE Serial Flash + * functionality. + */ + setbits32(spibar + SPIBAR_SFDP0_VSCC0, SPIBAR_VSCC0_VCL); +} + /* * Set FAST_SPIBAR Soft Reset Data Register value. */ diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index f28865d9b3..0be3dcd255 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -131,6 +131,13 @@ (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +/* + * Register Offset of BIOS Vendor Specific Component Capabilities (VSCC) + * for Component 0 Register + */ +#define SPIBAR_SFDP0_VSCC0 0xc4 +#define SPIBAR_VSCC0_VCL (1 << 30) + /* Bit definitions for PTINX (0xcc) register */ #define SPIBAR_PTINX_COMP_0 (0 << 14) #define SPIBAR_PTINX_COMP_1 (1 << 14) diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 1e96603438..90f1cb224e 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -42,6 +42,10 @@ void fast_spi_lock_bar(void); * FAST_SPI Protected Range (PR) registers. */ void fast_spi_pr_dlock(void); +/* + * Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30). + */ +void fast_spi_vscc0_lock(void); /* * Set FAST_SPIBAR Soft Reset Data Register value. */ -- cgit v1.2.3