From ae738acdc5f02d232e035538c67d63ba19b9ccaa Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sun, 24 Jul 2016 08:03:37 -0700 Subject: cpu/x86: Support CPUs without rdmsr/wrmsr instructions Quark does not support the rdmsr and wrmsr instructions. In this case use a SOC specific routine to support the setting of the MTRRs. Migrate the code from FSP 1.1 to be x86 CPU common. Since all rdmsr/wrmsr accesses are being converted, fix the build failure for quark in lib/reg_script.c. Move the soc_msr_x routines and their depencies from romstage/mtrr.c to reg_access.c. TEST=Build and run on Galileo Gen2 Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/15839 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/Kconfig | 7 ------- src/soc/intel/common/util.c | 14 +++++++------- src/soc/intel/common/util.h | 7 ------- 3 files changed, 7 insertions(+), 21 deletions(-) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 776004b1d6..a32252edd8 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -56,13 +56,6 @@ config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ No default is set here as this is an SOC-specific value and must be provided by the SOC when it selects this driver. -config SOC_SETS_MTRRS - bool - default n - help - The SoC needs uses different access methods for reading and writing - the MTRRs. Use SoC specific routines to handle the MTRR access. - config MMA bool "enable MMA (Memory Margin Analysis) support" default n diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c index 74ce9ff28f..2d3a34a63a 100644 --- a/src/soc/intel/common/util.c +++ b/src/soc/intel/common/util.c @@ -26,7 +26,7 @@ uint32_t soc_get_variable_mtrr_count(uint64_t *msr) msr_t s; } mtrrcap; - mtrrcap.s = soc_mtrr_read(MTRR_CAP_MSR); + mtrrcap.s = rdmsr(MTRR_CAP_MSR); if (msr != NULL) *msr = mtrrcap.u64; return mtrrcap.u64 & MTRR_CAP_VCNT; @@ -83,7 +83,7 @@ static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, msr_t s; } msr; - msr.s = soc_mtrr_read(msr_reg); + msr.s = rdmsr(msr_reg); printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x1000); } @@ -96,7 +96,7 @@ static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, msr_t s; } msr; - msr.s = soc_mtrr_read(msr_reg); + msr.s = rdmsr(msr_reg); printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x4000); } @@ -108,7 +108,7 @@ static void soc_display_64k_mtrr(void) msr_t s; } msr; - msr.s = soc_mtrr_read(MTRR_FIX_64K_00000); + msr.s = rdmsr(MTRR_FIX_64K_00000); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64); soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000); } @@ -136,7 +136,7 @@ static void soc_display_mtrr_def_type(void) msr_t s; } msr; - msr.s = soc_mtrr_read(MTRR_DEF_TYPE_MSR); + msr.s = rdmsr(MTRR_DEF_TYPE_MSR); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n", msr.u64, (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", @@ -160,8 +160,8 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index, msr_t s; } msr_m; - msr_a.s = soc_mtrr_read(msr_reg); - msr_m.s = soc_mtrr_read(msr_reg + 1); + msr_a.s = rdmsr(msr_reg); + msr_m.s = rdmsr(msr_reg + 1); if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { base_address = (msr_a.u64 & 0xfffffffffffff000ULL) & address_mask; diff --git a/src/soc/intel/common/util.h b/src/soc/intel/common/util.h index 7d05e47c1d..854f2b0657 100644 --- a/src/soc/intel/common/util.h +++ b/src/soc/intel/common/util.h @@ -22,12 +22,5 @@ asmlinkage void soc_display_mtrrs(void); uint32_t soc_get_variable_mtrr_count(uint64_t *msr); -#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) -msr_t soc_mtrr_read(unsigned long index); -void soc_mtrr_write(unsigned long index, msr_t msr); -#else -#define soc_mtrr_read rdmsr -#define soc_mtrr_write wrmsr -#endif /* CONFIG_SOC_SETS_MTRRS */ #endif /* _INTEL_COMMON_UTIL_H_ */ -- cgit v1.2.3