From abeb688154d9be5487403a65a74c8c24d380b3bf Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Mon, 7 Dec 2020 15:55:10 +0530 Subject: soc/intel/common: Check sizes of CSE CBFS RW blob and CSE RW BP The patch triggeres CrOS recovery mode if the sizes of CSE CBFS RW blob and CSE RW boot are different. TEST=Verified on drawcia. Signed-off-by: Sridhar Siricilla Change-Id: I8be589eae905b1a54a8cf981ccd3a00bd5e733f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48423 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Jamie Ryu Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cse/cse_lite.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index eb4be6edd0..8e89723334 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -74,6 +74,9 @@ enum csme_failure_reason { /* CSE CBFS RW metadata is not found */ CSE_LITE_SKU_RW_METADATA_NOT_FOUND = 10, + + /* CSE CBFS RW blob layout is not correct */ + CSE_LITE_SKU_LAYOUT_MISMATCH_ERROR = 11, }; /* @@ -674,6 +677,11 @@ static enum csme_failure_reason cse_update_rw(const struct cse_bp_info *cse_bp_i const void *cse_cbfs_rw, const size_t cse_blob_sz, struct region_device *target_rdev) { + if (region_device_sz(target_rdev) < cse_blob_sz) { + printk(BIOS_ERR, "RW update does not fit. CSE RW flash region size: %zx, Update blob size:%zx\n", + region_device_sz(target_rdev), cse_blob_sz); + return CSE_LITE_SKU_LAYOUT_MISMATCH_ERROR; + } if (!cse_erase_rw_region(target_rdev)) return CSE_LITE_SKU_FW_UPDATE_ERROR; -- cgit v1.2.3