From a25f310830b34aad29db712ab90b0d2c15ecbb2b Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Thu, 4 Apr 2024 20:02:31 +0100 Subject: intel/alderlake: Add helper functions for Power Management Clock Power Management, ASPM and L1 Substates have been configured the same way since Skylake. The main control to enable or disable is Kconfig, and then the level can be overridden in devicetree. Despite the UPDs remaining the same since Skylake, this is not the case for Alder Lake, Raptor Lake and Meteor Lake. Taking `starlabs/starbook` as an example, at the time of this commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE enabled. On Comet Lake, this results in the correct configuration, verified with the lspci command: ``` LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- ``` On Raptor Lake: ``` LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+ ``` Clock Power Management, ASPM and L1 Substates are also not configured for CPU root ports. Add helper functions to configure these correctly based on Kconfig, but retain the capability to override the specific levels from devicetree. Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/81638 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index dff4d97382..7f7dba6d31 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -37,6 +37,9 @@ enum pcie_clk_src_flags { PCIE_CLK_LAN = (1 << 1), }; +/* coreboot enums are off-by-1 to allow for no config in devicetree */ +#define UPD_INDEX(upd) (upd - 1) + /* This enum is for passing into an FSP UPD, typically PcieRpL1Substates */ enum L1_substates_control { L1_SS_FSP_DEFAULT, -- cgit v1.2.3