From 91da91f5d1ac3a1c2671771f18495fc3b703fae5 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 4 Sep 2015 13:47:34 -0700 Subject: intel/common: Print board ID if enabled Read and print the board ID if it is enabled in the mainboard. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I9d50089242b3a2f461dff2b1039adc8f0347179e Signed-off-by: Patrick Georgi Original-Commit-Id: f245854b30c40eda38453c1b0ae5d3b8b18c010f Original-Change-Id: Ifbd7c2666820ea146dc44fbc42bfe201cb227ff6 Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/297756 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11577 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/soc/intel/common/romstage.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c index 7a05e177f1..ee9c9751a8 100644 --- a/src/soc/intel/common/romstage.c +++ b/src/soc/intel/common/romstage.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -101,6 +102,13 @@ asmlinkage void *romstage_main(unsigned int bist, /* Perform SOC specific initialization. */ soc_romstage_init(¶ms); + /* + * Read and print board version. Done after SOC romstage + * in case PCH needs to be configured to talk to the EC. + */ + if (IS_ENABLED(CONFIG_BOARD_ID_AUTO)) + printk(BIOS_INFO, "MLB: board version %d\n", board_id()); + /* Call into mainboard. */ mainboard_romstage_entry(¶ms); soc_after_ram_init(¶ms); -- cgit v1.2.3