From 8c9a89de9961e7029835e987cb0f705b7efa77a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 6 Jun 2021 08:14:57 +0300 Subject: arch/x86/ioapic: Drop irq_on_fsb as a configurable item MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/lpc/lpc_lib.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 49509409e0..1b6936e508 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -290,12 +290,6 @@ void pch_enable_ioapic(void) reg32 |= (redir_entries - 1) << 16; io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); } static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = { -- cgit v1.2.3