From 7f9ceef51be785781ea4c0035c31d718d590a2fb Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Tue, 3 Mar 2020 20:15:02 +0100 Subject: intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable TCO SMIs in common code, if selected by Kconfig. This is needed for the follow-up commits regarding INTRUDER interrupt. Tested on X11SSM-F. Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39262 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/block/smm/smm.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index bef923ac1a..ecea473645 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -63,13 +63,16 @@ void smm_southbridge_enable(uint16_t pm1_events) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) * - on eSPI events, unless disabled (does nothing on LPC systems) + * - on TCO events (TIMEOUT, case intrusion, ...), if enabled * No SMIs: * - on microcontroller writes (io 0x62/0x66) - * - on TCO events */ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE)) smi_params &= ~ESPI_SMI_EN; + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)) + smi_params |= TCO_SMI_EN; + /* Enable SMI generation: */ pmc_enable_smi(smi_params); } -- cgit v1.2.3