From 3b70ad8ecfadcc393a15f98cbf476a34dd6b135c Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 9 Nov 2020 09:47:00 -0800 Subject: soc/intel/common: Use per-soc definition for BAR sizes The various platform BARs are not always the same size across different SOCs, so use the defined size rather than a hardcoded value. This results in the following change on TGL which increased the MCHBAR size to 128K: -system 00:00: [mem 0xfedc0000-0xfeddffff] has been reserved +system 00:00: [mem 0xfedc0000-0xfedc7fff] has been reserved And fixes the following error output from the kernel: resource sanity check: requesting [mem 0xfedc0000-0xfedcdfff], which spans more than pnp 00:00 [mem 0xfedc0000-0xfedc7fff] Change-Id: I82796c2fc81dec883f3c69ae7bdcedc7d3f16c64 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/47378 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/common/block/acpi/acpi/northbridge.asl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index bac059076a..b4b746542e 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -253,17 +253,17 @@ Device (PDRC) /* MCH BAR _BAS will be updated in _CRS below according to * B0:D0:F0:Reg.48h */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) + Memory32Fixed (ReadWrite, 0, MCH_BASE_SIZE, MCHB) /* DMI BAR _BAS will be updated in _CRS below according to * B0:D0:F0:Reg.68h */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) + Memory32Fixed (ReadWrite, 0, DMI_BASE_SIZE, DMIB) /* EP BAR _BAS will be updated in _CRS below according to * B0:D0:F0:Reg.40h */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) + Memory32Fixed (ReadWrite, 0, EP_BASE_SIZE, EGPB) /* PCI Express BAR _BAS and _LEN will be updated in * _CRS below according to B0:D0:F0:Reg.60h -- cgit v1.2.3