From 39bdb0bbcfebae1a7da1a51a7893541f31c4ed3d Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 4 Aug 2015 23:59:43 -0500 Subject: intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.c acpi_is_wakeup_s3() was introduced in upstream coreboot while the FSP support code was written. Move to using that instead of using the romstage_handoff structure directly. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I71601a4be3c981672e25e189c98abb6a676462bf Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/290720 Original-Reviewed-by: Leroy P Leahy Original-Reviewed-by: Duncan Laurie Change-Id: I2ae4d9906e0891080481fb58b941921922a989d3 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11190 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/common/fsp_ramstage.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c index b85591d7e1..5ccc4eea92 100644 --- a/src/soc/intel/common/fsp_ramstage.c +++ b/src/soc/intel/common/fsp_ramstage.c @@ -18,15 +18,16 @@ * Foundation, Inc. */ +#include #include #include #include #include #include -#include #include #include #include +#include #include /* SOC initialization after FSP silicon init */ @@ -176,7 +177,7 @@ static FSP_INFO_HEADER *soc_restore_support_code(void) return header->fih; } -static void fsp_run_silicon_init(struct romstage_handoff *handoff) +static void fsp_run_silicon_init(int is_s3_wakeup) { FSP_INFO_HEADER *fsp_info_header; FSP_SILICON_INIT fsp_silicon_init; @@ -209,7 +210,7 @@ static void fsp_run_silicon_init(struct romstage_handoff *handoff) /* Locate VBT and pass to FSP GOP */ if (IS_ENABLED(CONFIG_GOP_SUPPORT)) - load_vbt(handoff->s3_resume, &silicon_init_params); + load_vbt(is_s3_wakeup, &silicon_init_params); mainboard_silicon_init_params(&silicon_init_params); /* Display the UPD data */ @@ -305,11 +306,9 @@ static int fsp_find_and_relocate(void) void intel_silicon_init(void) { - struct romstage_handoff *handoff; + int is_s3_wakeup = acpi_is_wakeup_s3(); - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff != NULL && handoff->s3_resume) { + if (is_s3_wakeup) { printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); fsp_update_fih(soc_restore_support_code()); } else { @@ -318,7 +317,7 @@ void intel_silicon_init(void) fsp_cache_save(); } - fsp_run_silicon_init(handoff); + fsp_run_silicon_init(is_s3_wakeup); } /* Initialize the UPD parameters for SiliconInit */ -- cgit v1.2.3