From 32074149f702d988e07753b5ff5633dbd0e3409c Mon Sep 17 00:00:00 2001 From: robbie zhang Date: Thu, 1 Oct 2015 16:37:58 -0700 Subject: fsp/intel common: Add support for Gfx PEIM (AKA GOP) This patch provides the lb_framebuffer() for coreboot table with fsp gop usage, add Igd Opregion register defines, and update the UPD naming following fsp. BRANCH=none BUG=chrome-os-partner:44559 TEST=Built and boot on kunimitsu/glados. Change-Id: I9cf9d991eb09d698e7a78323cd855c4c99b55eca Signed-off-by: Patrick Georgi Original-Commit-Id: cd6834057cca60716bc0e24cfc2cd60fed02be7a Original-Change-Id: I64987e393c39a7cc1084edf59e7ca51b8c5ea743 Original-Signed-off-by: robbie zhang Original-Reviewed-on: https://chromium-review.googlesource.com/303539 Original-Commit-Ready: Robbie Zhang Original-Tested-by: Robbie Zhang Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/12141 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/common/gma.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h index 03ecedb5da..64b2a2811e 100644 --- a/src/soc/intel/common/gma.h +++ b/src/soc/intel/common/gma.h @@ -23,6 +23,12 @@ #include +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define GSSCIE (1 << 0) /* SCI Event trigger */ +#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ + /* mailbox 0: header */ typedef struct { u8 signature[16]; -- cgit v1.2.3