From 2ccc0a4d9fc91a57e1dec8913e6d999402e927a2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 25 Mar 2021 20:01:47 +0530 Subject: soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/common/acpi/gpio.asl | 4 ++-- src/soc/intel/common/acpi/platform.asl | 2 +- src/soc/intel/common/block/acpi/acpi/pep.asl | 2 +- src/soc/intel/common/block/gpio/gpio.c | 2 +- src/soc/intel/common/block/include/intelblocks/gpio.h | 8 ++++---- 5 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/acpi/gpio.asl b/src/soc/intel/common/acpi/gpio.asl index dbfa7af980..225f72a46f 100644 --- a/src/soc/intel/common/acpi/gpio.asl +++ b/src/soc/intel/common/acpi/gpio.asl @@ -11,8 +11,8 @@ Method (CGPM, 2, Serialized) Local0 = GPID (Arg0) If (Local0 != 0) { /* Mask off current PM bits */ - PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_ENABLE_GPIO_PM_CONFIG) + PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_GPIO_PM_CONFIG_BITS) /* Mask in requested bits */ - PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG) + PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_GPIO_PM_CONFIG_BITS) } } diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index a973149e6d..496f184278 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -30,7 +30,7 @@ Method (_PTS, 1) } /* * Save the current PM bits then - * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + * enable GPIO PM with MISCCFG_GPIO_PM_CONFIG_BITS */ If (CondRefOf (\_SB.PCI0.EGPM)) { diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl index b6a0d9d91a..2e2a25f279 100644 --- a/src/soc/intel/common/block/acpi/acpi/pep.asl +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -91,7 +91,7 @@ Device(PEPD) /* * Save the current PM bits then - * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + * enable GPIO PM with MISCCFG_GPIO_PM_CONFIG_BITS */ If (CondRefOf (\_SB.PCI0.EGPM)) { diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index c747f30c8a..417dfb88b2 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -656,7 +656,7 @@ void gpio_pm_configure(const uint8_t *misccfg_pm_values, size_t num) { int i; size_t gpio_communities; - const uint8_t misccfg_pm_mask = (uint8_t)~MISCCFG_ENABLE_GPIO_PM_CONFIG; + const uint8_t misccfg_pm_mask = (uint8_t)~MISCCFG_GPIO_PM_CONFIG_BITS; const struct pad_community *comm; comm = soc_gpio_get_community(&gpio_communities); diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 45ae1da4fd..3f79b19f94 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -6,6 +6,10 @@ #include #include "gpio_defs.h" +/* GPIO community IOSF sideband VNNREQ/ACK handshake */ +#define MISCCFG_GPVNNREQEN (1 << 7) +/* GPIO community PGCB clock gating */ +#define MISCCFG_GPPGCBDPCGEN (1 << 6) /* GPIO community IOSF sideband clock gating */ #define MISCCFG_GPSIDEDPCGEN (1 << 5) /* GPIO community RCOMP clock gating */ @@ -18,10 +22,6 @@ #define MISCCFG_GPDPCGEN (1 << 1) /* GPIO community local clock gating */ #define MISCCFG_GPDLCGEN (1 << 0) -/* Enable GPIO community power management configuration */ -#define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \ - MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \ - | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN) #ifndef __ACPI__ #include -- cgit v1.2.3