From 2276d4f4a858da4a1cccc7cd8d870f0ac114efed Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 28 Mar 2018 11:32:58 +0530 Subject: soc/intel/common: Add support to configure top swap feature RTC BUC control register provides a software interface to configure the top swap feature. This patch adds implementation to enable/disable top swap feature and gets it accessible in romstage as well. The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP is selected. To use the topswap feature a second bootblock has to be added to the cbfs. Below configs aid in doing that, INTEL_HAS_TOP_SWAP INTEL_ADD_TOP_SWAP_BOOTBLOCK INTEL_TOP_SWAP_BOOTBLOCK_SIZE Enabling and Disabling topswap, using the added API enables user to boot alternatively from either bootblock. Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad Signed-off-by: Aamir Bohra Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/25805 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- .../intel/common/block/include/intelblocks/rtc.h | 22 ++++++++++++++++++++++ src/soc/intel/common/block/rtc/Makefile.inc | 2 +- src/soc/intel/common/block/rtc/rtc.c | 18 ++++++++++++++++++ 3 files changed, 41 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/include/intelblocks/rtc.h b/src/soc/intel/common/block/include/intelblocks/rtc.h index c6507c84f9..56cfb2ea8c 100644 --- a/src/soc/intel/common/block/include/intelblocks/rtc.h +++ b/src/soc/intel/common/block/include/intelblocks/rtc.h @@ -16,6 +16,12 @@ #ifndef SOC_INTEL_COMMON_BLOCK_RTC_H #define SOC_INTEL_COMMON_BLOCK_RTC_H +/* Top swap feature enable/disable config */ +enum ts_config { + TS_DISABLE, + TS_ENABLE +}; + void enable_rtc_upper_bank(void); /* Expect return rtc failed bootlean in case of coin removal */ @@ -23,4 +29,20 @@ int soc_get_rtc_failed(void); void rtc_init(void); +/* + * set/unset RTC backed top swap bit in the BUC register. + * TS_ENABLE - PCH will invert A16, A17 or A18 for cycles + * going to the BIOS space based on PCH strap setting. + * TS_DISABLE - PCH will not invert A16, A17 or A18. + */ +void configure_rtc_buc_top_swap(enum ts_config ts_state); + +/* + * Return the current top swap state which is reflected by the + * RTC backed top swap bit in the BUC register. + * TS_ENABLE - Top swap enabled. + * TS_DISABLE - Top swap disabled. + */ +enum ts_config get_rtc_buc_top_swap_status(void); + #endif /* SOC_INTEL_COMMON_BLOCK_RTC_H */ diff --git a/src/soc/intel/common/block/rtc/Makefile.inc b/src/soc/intel/common/block/rtc/Makefile.inc index 95f665919d..aeb0d9431e 100644 --- a/src/soc/intel/common/block/rtc/Makefile.inc +++ b/src/soc/intel/common/block/rtc/Makefile.inc @@ -1,3 +1,3 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_RTC) += rtc.c - +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_RTC) += rtc.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_RTC) += rtc.c diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c index cb97953557..b8c8849d10 100644 --- a/src/soc/intel/common/block/rtc/rtc.c +++ b/src/soc/intel/common/block/rtc/rtc.c @@ -25,6 +25,9 @@ #define PCR_RTC_CONF_LCMOS_LOCK (1 << 3) #define PCR_RTC_CONF_UCMOS_LOCK (1 << 4) #define PCR_RTC_CONF_RESERVED (1 << 31) +/* RTC backed up control register */ +#define PCR_RTC_BUC 0x3414 +#define PCR_RTC_BUC_TOP_SWAP (1 << 0) void enable_rtc_upper_bank(void) { @@ -44,3 +47,18 @@ void rtc_init(void) cmos_init(soc_get_rtc_failed()); } + +#if IS_ENABLED(CONFIG_INTEL_HAS_TOP_SWAP) +void configure_rtc_buc_top_swap(enum ts_config ts_state) +{ + pcr_rmw32(PID_RTC, PCR_RTC_BUC, ~PCR_RTC_BUC_TOP_SWAP, ts_state); +} + +enum ts_config get_rtc_buc_top_swap_status(void) +{ + if (pcr_read32(PID_RTC, PCR_RTC_BUC) & PCR_RTC_BUC_TOP_SWAP) + return TS_ENABLE; + else + return TS_DISABLE; +} +#endif -- cgit v1.2.3