From 1d535eb467c3a9119ec3022494ded8b06bf7ab28 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Thu, 18 Jul 2024 21:08:30 +0100 Subject: soc/intel/cnvi: Add _S0W to ensure CNVi isn't put into D3 Cold All CNVi modules, integrated or dedicated only support D3 Hot so add _S0W to limit the sleep state. Intel document #559910 details this. Change-Id: I1541cebc022adc927a9cd883500320e9ef82359f Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/83558 Tested-by: build bot (Jenkins) Reviewed-by: Nicholas Sudsgaard --- src/soc/intel/common/block/cnvi/cnvi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 609c473341..afe08c5120 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -86,6 +86,18 @@ static void cnvw_fill_ssdt(const struct device *dev) acpigen_write_field("CWAR", fields2, ARRAY_SIZE(fields2), FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE); +/* + * Method (_S0W, 0, NotSerialized) // _S0W: S0 Device Wake State + * { + * Return (ACPI_DEVICE_SLEEP_D3_HOT) + * } + */ + acpigen_write_method("_S0W", 0); + { + acpigen_write_return_integer(ACPI_DEVICE_SLEEP_D3_HOT); + } + acpigen_pop_len(); + acpigen_write_scope_end(); } -- cgit v1.2.3