From 1ac0dc164d81f28602668cdb559b44f18dd4227d Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 2 Dec 2021 16:19:14 -0700 Subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Tiger Lake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59853 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Subrata Banik --- src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index f74706e9bf..ff10c51d43 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -117,4 +117,8 @@ enum pcie_rp_type { PCIE_RP_PCH, }; +/* For PCIe RTD3 support, each SoC that uses it must implement this function. */ +struct device; /* Not necessary to include all of device/device.h */ +enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev); + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ -- cgit v1.2.3