From 13cd3310a55c5683fb0b1176444ad8f5e5243945 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 7 Aug 2015 18:22:54 +0530 Subject: Braswell: Modify CB to accomodate new FSPv83 Latest FSPv83 made some change related to UPD/VPD need this patch to align those BUG=None TEST=Build and Boot Cyan System BRANCH=strago-7287.B CQ-DEPEND=CL:*226897 Original-Change-Id: I6395f3a1f4eecaef14fc4720b00252f9e6143fa3 Original-Signed-off-by: Subrata Banik Original-Reviewed-on: https://chromium-review.googlesource.com/291394 Original-Reviewed-by: Aaron Durbin Original-Tested-by: Hannah Williams Original-Commit-Queue: Hannah Williams Original-Reviewed-on: https://chromium-review.googlesource.com/303137 Original-Commit-Ready: John Zhao Original-Tested-by: John Zhao Change-Id: I9920eea84b802699454850bfde489668201ffeb6 Signed-off-by: Subrata Banik Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11813 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/common/vbt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index b12ec04712..3aba7c7c5d 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -47,5 +47,5 @@ void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params) } else vbt_data = NULL; } - params->PcdGraphicsConfigPtr = (u32)vbt_data; + params->GraphicsConfigPtr = (u32)vbt_data; } -- cgit v1.2.3