From 026f00476e11f6e9e53d19fba09d4d97c54e79cf Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Mon, 20 Jun 2022 08:09:29 +0100 Subject: soc/intel/common/pch: Add a block specific to Apollo Lake Add SOC_INTEL_COMMON_PCH_CLIENT which is specific to Apollo Lake. This is used to select the options that Apollo Lake requires, without the ones specific to a PCH as Apollo Lake doesn't have a PCH. This change also enables SOC_INTEL_COMMON_PCH_LOCKDOWN for Apollo Lake. Signed-off-by: Sean Rhodes Change-Id: I084a05f904a19f3b7e9a071636659670aa45bf3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65245 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/pch/Kconfig | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index f46b95dec9..4934bb0896 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -1,3 +1,11 @@ +config SOC_INTEL_INTEGRATED_SOUTHCLUSTER + bool + help + Apollo Lake and Gemini Lake are single-chip platforms with a south + cluster instead of a PCH. Most of the IP blocks are the same as in + PCH platforms, but there are several differences that need to be + accounted for. + config SOC_INTEL_COMMON_PCH_CLIENT bool select SOC_INTEL_COMMON_PCH_BASE @@ -33,24 +41,27 @@ config PCH_SPECIFIC_BASE_OPTIONS select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG - select SOC_INTEL_COMMON_BLOCK_GPMR select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_LPC - select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_RTC - select SOC_INTEL_COMMON_BLOCK_SATA select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TCO - select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_PCH_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_SMBUS +config PCH_SPECIFIC_DISCRETE_OPTIONS + def_bool !SOC_INTEL_INTEGRATED_SOUTHCLUSTER + select SOC_INTEL_COMMON_BLOCK_GPMR + select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR + select SOC_INTEL_COMMON_BLOCK_SATA + select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS + config PCH_SPECIFIC_CLIENT_OPTIONS def_bool SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_BLOCK_DSP -- cgit v1.2.3