From d0c00052d32ed2ea461811632197845120ca8a08 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 21 Nov 2016 09:19:53 -0800 Subject: soc/intel: Use correct terminology for SPI flash operations FPR is an attribute of the SPI flash component and not of the SPI bus itself. Rename functions, file names and Kconfig option to make sure this is conveyed correctly. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: I9f06f1a8ee28b8c56db64ddd6a19dd9179c54f50 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/17560 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/spi.h | 45 --------------------------------------------- 1 file changed, 45 deletions(-) delete mode 100644 src/soc/intel/common/spi.h (limited to 'src/soc/intel/common/spi.h') diff --git a/src/soc/intel/common/spi.h b/src/soc/intel/common/spi.h deleted file mode 100644 index a89f7925aa..0000000000 --- a/src/soc/intel/common/spi.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define SPI_FPR_SHIFT 12 -#define SPI_FPR_MASK 0x7fff -#define SPI_FPR_BASE_SHIFT 0 -#define SPI_FPR_LIMIT_SHIFT 16 -#define SPI_FPR_RPE (1 << 15) /* Read Protect */ -#define SPI_FPR_WPE (1 << 31) /* Write Protect */ -#define SPI_FPR(base, limit) \ - (((((limit) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_LIMIT_SHIFT) |\ - ((((base) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_BASE_SHIFT)) - -struct fpr_info { - /* Offset of first FPR register */ - uintptr_t base; - /* Maximum number of FPR registers */ - uint8_t max; -}; - -/* - * SoC is expected to implement this function to provide address of first FPR - * register and max count of FPR registers. - * - * On success return 0 else -1. - */ -int spi_get_fpr_info(struct fpr_info *info); - -/* - * Protect range of SPI flash defined by [start, start+size-1] using Flash - * Protected Range (FPR) register if available. - */ -int spi_flash_protect(u32 start, u32 size); -- cgit v1.2.3