From d2c57f2a0cdc3f07c2de278dfa4ae06bfb95f7bc Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Sun, 17 Jan 2021 03:11:40 +0100 Subject: soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the old, redundant code for mirroring LPC registers to DMI and make use of the new common code. Select the new Kconfig option for LPC DMI mirroring by the option SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig directly. APL, even though it's younger than SPT, does not need mirroring. Test: Set LGMR address by calling `lpc_open_mmio_window` and check that both the PCI cfg and DMI LGMR register get written correctly. Tested successfully on clevo/cml-u. Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/common/pch/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/common/pch') diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index b00fc8bb71..644fed1f4d 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -27,6 +27,7 @@ config PCH_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_I2C select SOC_INTEL_COMMON_BLOCK_LPC + select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PCIE -- cgit v1.2.3