From 8dcd62d705fb3058f7c36e554840c3df69f244ce Mon Sep 17 00:00:00 2001
From: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Date: Wed, 2 Dec 2020 17:20:24 -0800
Subject: soc/intel/common/dmi: Add support for locking down SRL

This change adds support to lock down the DMI configuration
in dmi_lockdown_cfg() by setting Secure Register Lock (SRL)
bit in DMI control register.

BUG=b:171534504

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48258
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/pch/lockdown/lockdown.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'src/soc/intel/common/pch/lockdown/lockdown.c')

diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c
index b10306edcb..d9495a432b 100644
--- a/src/soc/intel/common/pch/lockdown/lockdown.c
+++ b/src/soc/intel/common/pch/lockdown/lockdown.c
@@ -2,6 +2,7 @@
 
 #include <bootstate.h>
 #include <intelblocks/cfg.h>
+#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/pcr.h>
 #include <intelpch/lockdown.h>
@@ -9,9 +10,6 @@
 #include <soc/pcr_ids.h>
 #include <soc/soc_chip.h>
 
-#define PCR_DMI_GCS		0x274C
-#define PCR_DMI_GCS_BILD	(1 << 0)
-
 /*
  * This function will get lockdown config specific to soc.
  *
@@ -40,6 +38,12 @@ static void dmi_lockdown_cfg(void)
 	 *	"1b": LPC/eSPI
 	 */
 	pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
+
+	/*
+	 * Set Secure Register Lock (SRL) bit in DMI control register to lock
+	 * DMI configuration.
+	 */
+	pcr_or32(PID_DMI, PCR_DMI_DMICTL, PCR_DMI_DMICTL_SRLOCK);
 }
 
 static void fast_spi_lockdown_cfg(int chipset_lockdown)
-- 
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