From 63afea54f41cb6054d8a3625238424e381a4fada Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 25 Nov 2020 01:07:06 -0800 Subject: soc/intel/common/dmi: Add DMI driver support This change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding in DMI. This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 3. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47988 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/soc/intel/common/pch/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/common/pch/Kconfig') diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index cca65d6b2a..b00fc8bb71 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -19,6 +19,7 @@ config PCH_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_DSP + select SOC_INTEL_COMMON_BLOCK_DMI select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG -- cgit v1.2.3