From 0946ec37aa4660ecf16d66cb1174a68df0afc4f0 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Mon, 20 Apr 2015 15:24:54 -0700 Subject: Intel Common SOC: Add romstage support Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/mrc_cache.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/common/mrc_cache.c') diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 6783f18fe3..9a066d533f 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -154,7 +154,7 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache) return __mrc_cache_get_current(®ion, cache); } -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE /* * romstage code @@ -331,4 +331,4 @@ static void update_mrc_cache(void *unused) BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif /* defined(__PRE_RAM__) */ +#endif /* ENV_ROMSTAGE */ -- cgit v1.2.3