From e7264110a6b32f9949a8e4a533548b903e041352 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 20 Nov 2024 05:39:27 +0000 Subject: soc/intel/cmn/acpi: Use Kconfig guards for UFS workarounds This change introduces Kconfig guards around the UFS workaround code in the common ACPI ASL file. This ensures that these workarounds are only applied when necessary, allowing future SoCs with UFS controllers to reuse the common ASL file without modification. By using Kconfig, we can enable or disable the workarounds based on the specific SoC configuration, providing greater flexibility and maintainability. BUG=b:379828045 TEST=Able to compile google/fatcat. Change-Id: I968b8811e508378a36648bd8234ff0fd7237b00d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/85208 Reviewed-by: Pranava Y N Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/acpi/acpi/ufs.asl | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/common/block') diff --git a/src/soc/intel/common/block/acpi/acpi/ufs.asl b/src/soc/intel/common/block/acpi/acpi/ufs.asl index fcfe9bd470..7d8d25dc41 100644 --- a/src/soc/intel/common/block/acpi/acpi/ufs.asl +++ b/src/soc/intel/common/block/acpi/acpi/ufs.asl @@ -28,6 +28,7 @@ Scope (\_SB.PCI0) } }) +#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE) /* * OCP Timer need to be disabled in SCS UFS IOSF Bridge to work around * the Silicon Issue due to which LTR mechanism doesn't work. @@ -47,6 +48,7 @@ Scope (\_SB.PCI0) PCRA (PID_UFSX2, R_SCS_PCR_5820, 0x0) PCRA (PID_UFSX2, R_SCS_PCR_1078, 0x0) } +#endif /* Memory Region to access to the UFS PCI Configuration Space */ OperationRegion(SCSR, PCI_Config, 0x00, 0x100) @@ -62,6 +64,7 @@ Scope (\_SB.PCI0) PGEN, 1 } +#if CONFIG(SOC_INTEL_UFS_LTR_DISQUALIFY) OperationRegion(PWMR, SystemMemory, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE) Field(PWMR, DWordAcc, NoLock, Preserve) { @@ -73,6 +76,7 @@ Scope (\_SB.PCI0) Method (ULTR, 1, Serialized) { LTRU = Arg0 } +#endif Method (_PS0, 0, Serialized) { -- cgit v1.2.3