From da527ec12b01d4794c2b99576dc49bfedadac767 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 24 Nov 2022 15:42:35 +0530 Subject: soc/intel/cmn/cse: Create API to get CSE Lite WP Information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch creates an API for CSE-Lite specific SKU to retrieve the Write Protect (WP) information (`cse_log_ro_write_protection_info`) like WP range and limit, if the region is write-protected or not etc. BUG=none TEST=Able to compile the cse_lite.c file for google/kano without any error. Signed-off-by: Subrata Banik Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968 Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/soc/intel/common/block/cse/cse_lite.c | 23 ++++++++++++++++++++++ .../intel/common/block/include/intelblocks/cse.h | 3 +++ 2 files changed, 26 insertions(+) (limited to 'src/soc/intel/common/block') diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index f051061e7d..37640f43f6 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -133,6 +134,28 @@ struct get_bp_info_rsp { static const char * const cse_regions[] = {"RO", "RW"}; +void cse_log_ro_write_protection_info(bool mfg_mode) +{ + bool cse_ro_wp_en = is_spi_wp_cse_ro_en(); + + printk(BIOS_DEBUG, "ME: WP for RO is enabled : %s\n", + cse_ro_wp_en ? "YES" : "NO"); + + if (cse_ro_wp_en) { + uint32_t base, limit; + spi_get_wp_cse_ro_range(&base, &limit); + printk(BIOS_DEBUG, "ME: RO write protection scope - Start=0x%X, End=0x%X\n", + base, limit); + } + + /* + * If manufacturing mode is disabled, but CSE RO is not write protected, + * log error. + */ + if (!mfg_mode && !cse_ro_wp_en) + printk(BIOS_ERR, "ME: Write protection for CSE RO is not enabled\n"); +} + bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp) { struct cse_boot_perf_req { diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f7aae1c0cd..cceee4f8ac 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -555,4 +555,7 @@ void soc_disable_heci1_using_pcr(void); */ void cse_get_telemetry_data(void); +/* Function to log the cse WP information like range, if WP etc. */ +void cse_log_ro_write_protection_info(bool mfg_mode); + #endif // SOC_INTEL_COMMON_CSE_H -- cgit v1.2.3