From cc05e311a26132abe3139d4c5f2bc36db5a738d1 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 18 Sep 2020 01:34:27 -0600 Subject: soc/intel/common/cse_lite: Defer cse_fw_sync for JSL Defer cse_fw_sync to BS_DEV_RESOURCES boot state so that MRC training data can be cached before CSE FW Sync and a second MRC training can be avoided. BUG=b:168850641 TEST=Build and boot the waddledoo board to OS. Ensure that the memory training is performed only once. Change-Id: I0ef5693eaa6ed34dc08c94e5db153f4295578f5f Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/45515 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Sridhar Siricilla Reviewed-by: Rizwan Qureshi --- src/soc/intel/common/block/cse/cse_lite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/common/block') diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 7daa35eb9b..c9e4e1f470 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -751,7 +751,7 @@ void cse_fw_sync(void *unused) } } -#if CONFIG(SOC_INTEL_TIGERLAKE) +#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE) /* * This needs to happen after the MRC cache write to avoid a 2nd * memory training sequence. -- cgit v1.2.3