From cb06fab1fcb17cf9fd82b2d74c2eb2e319f2bba2 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Wed, 20 Dec 2017 17:18:01 -0800 Subject: soc/intel/common/block/gspi: set cs polarity before using Move call to __gspi_cs_change() in gspi_ctrlr_setup() to after initialization of cs polarity since it requires polarity to be set to work properly. Failure to do so confuses cr50. BUG=b:70628116 BRANCH=chromeos-2016.05 TEST='emerge-meowth coreboot' and verify on scope that chip select polarity is correct for the first transaction. Change-Id: I20b4f584663477d751a07889bccc865efbf9c469 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/25013 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Caveh Jalali Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/gspi/gspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/common/block') diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 2f574a4eb9..60c7391ad0 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -414,9 +414,6 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) /* Take controller out of reset, keeping DMA in reset. */ gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET); - /* De-assert chip select. */ - __gspi_cs_change(p, CS_DEASSERT); - /* * CS control: * - Set SW mode. @@ -430,6 +427,9 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT); gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl); + /* De-assert chip select. */ + __gspi_cs_change(p, CS_DEASSERT); + /* Disable SPI controller. */ gspi_write_mmio_reg(p, SSCR0, SSCR0_SSE_DISABLE); -- cgit v1.2.3