From 6d569163ab680ca436b16c040e6840e969df6c61 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 10 Apr 2019 12:19:27 +0530 Subject: soc/intel/cpulib: Remove redundent enable/disable functions This patch removes multiple enable/disable function definitions and make use of single function with argument to know feature status (enable/disable). Change-Id: I502cd2497b07e9de062df453ecbb9c11df692f5a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32282 Reviewed-by: Arthur Heymans Reviewed-by: Lijian Zhao Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cpu/cpulib.c | 46 ++++++++-------------- .../common/block/include/intelblocks/cpulib.h | 22 ++++------- 2 files changed, 24 insertions(+), 44 deletions(-) (limited to 'src/soc/intel/common/block') diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 9964f2b02c..a7f89baafd 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -185,50 +185,36 @@ int cpu_get_burst_mode_state(void) } /* - * Enable Burst mode. + * Program CPU Burst mode + * true = Enable Burst mode. + * false = Disable Burst mode. */ -void cpu_enable_burst_mode(void) +void cpu_burst_mode(bool burst_mode_status) { msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.hi &= ~BURST_MODE_DISABLE; + if (burst_mode_status) + msr.hi &= ~BURST_MODE_DISABLE; + else + msr.hi |= BURST_MODE_DISABLE; wrmsr(IA32_MISC_ENABLE, msr); } /* - * Disable Burst mode. + * Program Enhanced Intel Speed Step Technology + * true = Enable EIST. + * false = Disable EIST. */ -void cpu_disable_burst_mode(void) +void cpu_set_eist(bool eist_status) { msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.hi |= BURST_MODE_DISABLE; - wrmsr(IA32_MISC_ENABLE, msr); -} - -/* - * Enable Intel Enhanced Speed Step Technology. - */ -void cpu_enable_eist(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); -} - -/* - * Disable Intel Enhanced Speed Step Technology. - */ -void cpu_disable_eist(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ + if (eist_status) + msr.lo |= (1 << 16); + else + msr.lo &= ~(1 << 16); wrmsr(IA32_MISC_ENABLE, msr); } diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 5cea96e409..70ad253607 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -97,24 +97,18 @@ enum { int cpu_get_burst_mode_state(void); /* - * Enable Burst mode. + * Program CPU Burst mode + * true = Enable Burst mode. + * false = Disable Burst mode. */ -void cpu_enable_burst_mode(void); +void cpu_burst_mode(bool burst_mode_status); /* - * Disable Burst mode. + * Program Enhanced Intel Speed Step Technology + * true = Enable EIST. + * false = Disable EIST. */ -void cpu_disable_burst_mode(void); - -/* - * Enable Intel Enhanced Speed Step Technology. - */ -void cpu_enable_eist(void); - -/* - * Disable Intel Enhanced Speed Step Technology. - */ -void cpu_disable_eist(void); +void cpu_set_eist(bool eist_status); /* * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120 -- cgit v1.2.3