From 4cba419676de40c76e4979957baf6039da8b8bf5 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 1 Sep 2020 16:10:06 -0600 Subject: soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP The IA32_MTRR_CAP register has a bit which indicates that the SMRR MSRs can be "locked" and this patch adds the definition for that. BUG=b:164489598 Signed-off-by: Tim Wawrzynczak Change-Id: I1254fb40c790f2a83dd11c2aabcf9bdf922b9395 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45012 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Subrata Banik Reviewed-by: Angel Pons --- src/soc/intel/common/block/include/intelblocks/msr.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/common/block') diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 82874f9224..4aa069e068 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -106,8 +106,9 @@ #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) /* MTRR_CAP_MSR bits */ -#define SMRR_SUPPORTED (1<<11) -#define PRMRR_SUPPORTED (1<<12) +#define SMRR_SUPPORTED (1<<11) +#define PRMRR_SUPPORTED (1<<12) +#define SMRR_LOCK_SUPPORTED (1<<14) #define SGX_SUPPORTED (1<<2) /* Intel SDM: Table 36-6. -- cgit v1.2.3