From 4a1cbdd51aafa671ecb6c93a475ca9bf6f9ca914 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 28 Nov 2020 19:47:41 -0800 Subject: soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry This change drops the special check added for TGL/JSL platforms and performs cse_fw_sync on BS_PRE_DEVICE entry. This was being done later in the boot process to ensure that the memory training parameters are written back to SPI flash before performing a reset for CSE RW jump. With the recent changes in CB:44196 ("mrc_cache: Update mrc_cache data in romstage"), MRC cache is updated right away in romstage. So, CSE RW jump can be performed in BS_PRE_DEVICE phase. Signed-off-by: Furquan Shaikh Change-Id: I947a40cd9776342d2067c9d5a366358917466d58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48130 Tested-by: build bot (Jenkins) Reviewed-by: Sridhar Siricilla Reviewed-by: Duncan Laurie Reviewed-by: Jamie Ryu --- src/soc/intel/common/block/cse/cse_lite.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'src/soc/intel/common/block') diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 9c498b536f..9011593417 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -809,12 +809,4 @@ void cse_fw_sync(void *unused) } } -#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE) -/* - * This needs to happen after the MRC cache write to avoid a 2nd - * memory training sequence. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL); -#else BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); -#endif -- cgit v1.2.3