From 419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 1 Oct 2018 08:47:51 +0200 Subject: src: Move common IA-32 MSRs to Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth Reviewed-by: Lijian Zhao Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cpu/car/cache_as_ram.S | 17 +++++++++-------- src/soc/intel/common/block/cpu/car/exit_car.S | 5 +++-- src/soc/intel/common/block/cpu/cpulib.c | 6 +++--- src/soc/intel/common/block/include/intelblocks/msr.h | 19 +------------------ src/soc/intel/common/block/sgx/sgx.c | 2 +- src/soc/intel/common/block/vmx/vmx.c | 4 ++-- 6 files changed, 19 insertions(+), 34 deletions(-) (limited to 'src/soc/intel/common/block') diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 684f82786a..17b8dc063c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -306,7 +307,7 @@ car_cqos: wrmsr /* Set CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */ wrmsr @@ -339,7 +340,7 @@ car_cqos: post_code(0x27) /* Cache is populated. Use mask 1 that will block evicts */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */ or $1, %edx /* select mask 1 */ @@ -410,7 +411,7 @@ find_llc_subleaf: */ shl %cl, %eax subl $0x02, %eax - movl $MSR_IA32_L3_MASK_1, %ecx + movl $IA32_L3_MASK_1, %ecx xorl %edx, %edx wrmsr /* @@ -419,12 +420,12 @@ find_llc_subleaf: * For SKL SOC, data size remains 256K consistently. * Hence, creating 1-way associative cache for Data */ - mov $MSR_IA32_L3_MASK_2, %ecx + mov $IA32_L3_MASK_2, %ecx mov $0x01, %eax xorl %edx, %edx wrmsr /* - * Set MSR_IA32_PQR_ASSOC = 0x02 + * Set IA32_PQR_ASSOC = 0x02 * * Possible values: * 0: Default value, no way mask should be applied @@ -432,7 +433,7 @@ find_llc_subleaf: * 2: Apply way mask 2 to LLC * 3: Shouldn't be use in NEM Mode */ - movl $MSR_IA32_PQR_ASSOC, %ecx + movl $IA32_PQR_ASSOC, %ecx movl $0x02, %eax xorl %edx, %edx wrmsr @@ -444,11 +445,11 @@ find_llc_subleaf: cld rep stosl /* - * Set MSR_IA32_PQR_ASSOC = 0x01 + * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache. * i.e. way 0 is protected from eviction. */ - movl $MSR_IA32_PQR_ASSOC, %ecx + movl $IA32_PQR_ASSOC, %ecx movl $0x01, %eax xorl %edx, %edx wrmsr diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 86feddca43..a4d16e8022 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -15,6 +15,7 @@ */ #include +#include #include #include @@ -80,7 +81,7 @@ car_cqos_teardown: wrmsr /* Reset CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr @@ -101,7 +102,7 @@ car_nem_enhanced_teardown: wrmsr /* Reset CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 112a0496a0..ebbdabd3e8 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -95,7 +95,7 @@ void cpu_set_p_state_to_turbo_ratio(void) perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -115,7 +115,7 @@ void cpu_set_p_state_to_nominal_tdp_ratio(void) perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -135,7 +135,7 @@ void cpu_set_p_state_to_max_non_turbo_ratio(void) perf_ctl.lo = msr.lo & 0xff00; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 154f03b81e..63b92013a3 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -17,13 +17,6 @@ #define SOC_INTEL_COMMON_MSR_H #define MSR_CORE_THREAD_COUNT 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define FEATURE_CONTROL_LOCK (1) -#define FEATURE_ENABLE_VMX (1 << 2) -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -#define SGX_GLOBAL_ENABLE (1 << 18) -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 /* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ @@ -46,16 +39,13 @@ #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) -#define IA32_MCG_CAP 0x179 #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define MSR_IA32_PERF_CTL 0x199 -#define IA32_MISC_ENABLE 0x1a0 -/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */ +/* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ #define BURST_MODE_DISABLE (1 << 6) #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_PREFETCH_CTL 0x1a4 @@ -76,8 +66,6 @@ #define MSR_EVICT_CTL 0x2e0 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 -#define IA32_MC0_CTL 0x400 -#define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) #define MSR_PKG_POWER_SKU_UNIT 0x606 @@ -122,11 +110,6 @@ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -#define MSR_IA32_PQR_ASSOC 0x0c8f -/* MSR bits 33:32 encode slot number 0-3 */ -#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) -#define MSR_IA32_L3_MASK_1 0x0c91 -#define MSR_IA32_L3_MASK_2 0x0c92 #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) /* MTRR_CAP_MSR bits */ diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index daedcfcf5d..6050dec093 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -137,7 +137,7 @@ static void enable_sgx(void) msr = rdmsr(IA32_FEATURE_CONTROL); /* Only enable it when it is not locked */ - if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) { + if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) { msr.lo |= SGX_GLOBAL_ENABLE; /* Enable it */ wrmsr(IA32_FEATURE_CONTROL, msr); } diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c index 591ffbc6df..2cffdabd2e 100644 --- a/src/soc/intel/common/block/vmx/vmx.c +++ b/src/soc/intel/common/block/vmx/vmx.c @@ -58,7 +58,7 @@ void vmx_configure(void *unused) msr = rdmsr(IA32_FEATURE_CONTROL); /* Only enable it when it is not locked */ - if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) { + if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) { /* Enable VMX */ msr.lo |= FEATURE_ENABLE_VMX; wrmsr(IA32_FEATURE_CONTROL, msr); @@ -68,5 +68,5 @@ void vmx_configure(void *unused) msr = rdmsr(IA32_FEATURE_CONTROL); printk(BIOS_DEBUG, "VMX status: %s, %s\n", (msr.lo & FEATURE_ENABLE_VMX) ? "enabled" : "disabled", - (msr.lo & FEATURE_CONTROL_LOCK) ? "locked" : "unlocked"); + (msr.lo & FEATURE_CONTROL_LOCK_BIT) ? "locked" : "unlocked"); } -- cgit v1.2.3