From 403458e7ec0fae1345cd82128b71d5ab0b66fd77 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 22 Aug 2018 13:03:55 +0200 Subject: siemens/mc_apl1: Extend circuit life by clock gating and power gating The firmware of devices connected to LPC should deassert the LPC CLKRUN# signal when there is no bus activity on LPC. Necessary changes: - Enable LPC CLKRUN# - Enable LPC PCE (Power Control Enable) - Enable LPC CCE (Clock Control Enable) - Remove I/O decoding range on LPC for COM 3 - Disable I/O UART driver Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/28268 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- src/soc/intel/common/block/include/intelblocks/lpc_lib.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/common/block') diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index ba4f045c34..e7b844fc4a 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017-2018 Intel Corp. + * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -47,6 +48,11 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 +/* LPC PCR configuration */ +#define PCR_LPC_PRC 0x341c +#define PCR_LPC_CCE_EN 0xf +#define PCR_LPC_PCE_EN (9 << 8) + /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ enum serirq_mode { SERIRQ_QUIET, -- cgit v1.2.3