From 3d802535cbf222d403e0d7d5cc6632546333a4c4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 12 Nov 2020 21:17:56 +0100 Subject: soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes coreboot in control of these settings. Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47537 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/soc/intel/common/block/p2sb/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/common/block') diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc index a1330abdd9..d557e36833 100644 --- a/src/soc/intel/common/block/p2sb/Makefile.inc +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c -- cgit v1.2.3