From 0d34a50a360228138ade623e799b03eaba83b0a5 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 31 Dec 2022 18:27:22 -0700 Subject: src: Move POST_BOOTBLOCK_CAR to common postcodes and use it This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific postcodes into the common postcode list, and uses it for the cache-as-RAM init as needed. Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in most of the others, the values were consolidated into 0x21. This will change the value on some platforms. Any conflicts should get sorted out later in the conversion process. Signed-off-by: Martin Roth Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas --- src/soc/intel/common/block/include/intelblocks/post_codes.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/soc/intel/common/block') diff --git a/src/soc/intel/common/block/include/intelblocks/post_codes.h b/src/soc/intel/common/block/include/intelblocks/post_codes.h index d7c0ef1cfa..7c78ef8e0e 100644 --- a/src/soc/intel/common/block/include/intelblocks/post_codes.h +++ b/src/soc/intel/common/block/include/intelblocks/post_codes.h @@ -16,9 +16,6 @@ #define POST_SOC_CAR_INIT_DONE 0x29 #define POST_SOC_BEFORE_CARSTAGE 0x2a -/* common/block/cpu/car/cache_as_ram_fsp.S */ -#define POST_BOOTBLOCK_CAR 0x21 - /* common/block/cse/cse.c */ #define POST_CODE_ZERO 0x00 #endif -- cgit v1.2.3