From a8198eb9ad1daea7b88ffa1d995907783a7c13c3 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 4 Aug 2017 16:12:19 -0700 Subject: soc/intel/common/uart: Add support for enabling UART debug controller on resume It has been observed on a number of platforms (baytrail, kaby lake) that if serial console is not enabled in coreboot, but is enabled in kernel (v4.4), then on resume kernel hangs. In order to fix this, add support for enabling UART debug port controller on resume. In order to decide whether UART debug port controller should be enabled in ramstage, following things are checked in given order: 1. If coreboot has serial console enabled, there is no need to re-initialize the controller. 2. This special action is taken only for UART debug port controller. 3. If boot is not S3 resume, then initialization is skipped. 4. Callback into SoC to check if it wants to initialize the controller. If all the above conditions are met, then UART debug port controller is initialized and taken out of reset. BUG=b:64030366 TEST=Verified with the entire patchset series that: 1. If coreboot does not have serial console enabled, but Linux kernel has console enabled, then on resume, coreboot initializes UART debug port controller. 2. If coreboot and Linux do not have serial console enabled, then coreboot does not initialize UART debug port controller. 3. If coreboot has serial console enabled, there is no change in behavior. Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/20835 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- src/soc/intel/common/block/uart/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/common/block/uart/Makefile.inc') diff --git a/src/soc/intel/common/block/uart/Makefile.inc b/src/soc/intel/common/block/uart/Makefile.inc index 1a2c8be933..348b153907 100644 --- a/src/soc/intel/common/block/uart/Makefile.inc +++ b/src/soc/intel/common/block/uart/Makefile.inc @@ -1,2 +1,3 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c -- cgit v1.2.3