From 047cac7b42eaf5b799e653ed1cc4a1b13e3f95e4 Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Wed, 29 May 2019 23:38:15 +0530 Subject: soc/intel/common/block: Enable PCH Thermal Sensor for threshold configuration PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE. Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685 Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/33129 Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/thermal/Makefile.inc | 1 + 1 file changed, 1 insertion(+) create mode 100644 src/soc/intel/common/block/thermal/Makefile.inc (limited to 'src/soc/intel/common/block/thermal/Makefile.inc') diff --git a/src/soc/intel/common/block/thermal/Makefile.inc b/src/soc/intel/common/block/thermal/Makefile.inc new file mode 100644 index 0000000000..6f216b3f33 --- /dev/null +++ b/src/soc/intel/common/block/thermal/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c -- cgit v1.2.3