From 2ec1c13ac4a9724095ce71783fd52f70a0b1536d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 09:57:05 +0200 Subject: soc/intel/common: Fix 16-bit read/write PCI_COMMAND register Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/common/block/smm/smihandler.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/common/block/smm') diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 44fe59d2c9..d8127a8c67 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -139,7 +139,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); @@ -152,9 +152,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If it's not a bridge, move on. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); -- cgit v1.2.3