From 2ccbcc560f01a7cd646b5012c3f680623c43ef96 Mon Sep 17 00:00:00 2001 From: Tim Chu Date: Thu, 8 Dec 2022 11:05:36 +0000 Subject: soc/intel/cmn/block: Add smbus/p2sb device ids for SPR-SP Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched on Jan. 10, 2023. The chipset includes Emmitsburg PCH. Signed-off-by: Tim Chu Change-Id: I05ed8f753bf63b6cb3035e973eb6a7974edfd673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71944 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/soc/intel/common/block/smbus/smbus.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/common/block/smbus/smbus.c') diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 6d6e8c8c42..d482e26847 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -56,6 +56,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_GLK_SMBUS, PCI_DID_INTEL_CNL_SMBUS, PCI_DID_INTEL_CNP_H_SMBUS, + PCI_DID_INTEL_EBG_SMBUS, PCI_DID_INTEL_LWB_SMBUS_SUPER, PCI_DID_INTEL_LWB_SMBUS, PCI_DID_INTEL_ICP_LP_SMBUS, -- cgit v1.2.3