From b7fe7a1a8e033706f39c0fded5901f0f1dce7cfb Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Thu, 8 Mar 2018 16:32:43 -0800 Subject: intel/common/block/scs: Add ability to send early CMD0, CMD1 In order to improve boot time with emmc, add ability to send CMD0 and CMD1 early in romstage. This way, by the time system boots to payload, we are ready to continue with emmc setup and we don't need to send CMD0 in payload again, and wait for card to reset and be ready. BUG=b:78106689 TESTS = Boot to OS Force early_mmc_wake_hw() to return error, recover in payload Force an error in payload, make sure system can recover/boot Change-Id: I3488b077bf5100a1e0f2c879fb1436105607d25e Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/25068 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/soc/intel/common/block/scs/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/soc/intel/common/block/scs/Kconfig') diff --git a/src/soc/intel/common/block/scs/Kconfig b/src/soc/intel/common/block/scs/Kconfig index 0a402137bc..06ad8e4fa8 100644 --- a/src/soc/intel/common/block/scs/Kconfig +++ b/src/soc/intel/common/block/scs/Kconfig @@ -2,3 +2,13 @@ config SOC_INTEL_COMMON_BLOCK_SCS bool help Intel Processor common storage and communication subsystem support + +config SOC_INTEL_COMMON_EARLY_MMC_WAKE + bool + default n + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_MMC + select SDHCI_CONTROLLER + help + Send CMD1 early in romstage to improve boot time. It requires emmc + DLL tuning parameters to be added to devicetree.cb -- cgit v1.2.3