From 8ed5835a1492070fb163ba79db892bd9c0df149e Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 22 Oct 2022 22:17:28 +0200
Subject: soc/intel/common: Clean up includes

Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
---
 src/soc/intel/common/block/pcie/pcie.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src/soc/intel/common/block/pcie')

diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index d3fcbde38d..dd0b0ef989 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -1,11 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
+#include <device/device.h>
 #include <device/pci.h>
-#include <device/pciexp.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <device/pciexp.h>
+#include <stdint.h>
 
 #define CACHE_LINE_SIZE	0x10
 
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