From cd49cce7b70e80b4acc49b56bb2bb94370b4d867 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 5 Mar 2019 16:53:33 -0800 Subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/common/block/pcie/pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/common/block/pcie/pcie.c') diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index c191ad06cd..0a5e1bf4d6 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -46,7 +46,7 @@ static void pch_pcie_init(struct device *dev) /* disable parity error response, enable ISA */ pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2); - if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) { + if (CONFIG(PCIE_DEBUG_INFO)) { printk(BIOS_SPEW, " MBL = 0x%08x\n", pci_read_config32(dev, PCI_MEMORY_BASE)); printk(BIOS_SPEW, " PMBL = 0x%08x\n", -- cgit v1.2.3