From 571d07d45b51d1b20af29cad27390b83b82f0aba Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Thu, 22 Aug 2019 13:11:32 +0300 Subject: soc/intel/skylake: Add Lewisburg family PCH support This patch adds Lewisburg C62x Series PCH support by adding the Production and Super SKUs of the following PCI devices: - LPC or eSPI Controllers, - PCI Express Root Ports, - SSATA and SATA Controllers, - SMBus, - SPI Controller, - ME/HECI, - Audio, - P2SB, - Power Management Controller. These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/35030 Tested-by: build bot (Jenkins) Reviewed-by: Lance Zhao --- src/soc/intel/common/block/pcie/pcie.c | 40 ++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'src/soc/intel/common/block/pcie/pcie.c') diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index e8b1050f4a..94fa63122e 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -113,6 +113,46 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18, PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19, PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20_SUPER, PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1, PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2, PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3, -- cgit v1.2.3